The present invention relates to an asynchronous circuit description language and the computer program product that enables those engineers who are well versed in hardware description languages (HDLs) to capture, verify and synthesize asynchronous circuit designs.
Along a phenomenal increase in the scale of circuits enabled by the rapid progress of technology, text-base techniques for capturing, verifying and synthesizing circuit designs by using HDLs have come in common. The phenomenal increase in the scale of circuit was instrumental in spreading the synchronous design technique, wherein all circuits are driven by a global clock, as a standard technique in a very short term. The CAE/CAD tools, SSI and MSI parts, cell libraries, and the like are all prepared almost only for synchronous designs. However, recently the clock skew problem came up along with deep sub-micron technologies, large-area VLSI chips and increasing clock frequencies. Through the scaling down of deep sub-micron technologies, wire delay is getting relatively larger while switching delay is getting smaller. As a result, the delays of the clock signal arrivals at the elements deviate widely depending on the traveling distances of the clock wires between the clock driver and the elements, so that the integrity of input/output signals of elements driven by the deviating global signal can not be guaranteed any longer. In addition to the problem of clock skew, increasing power consumption is also becoming a large problem. Exponentially increasing power consumption of VLSI, which is caused by high-speed switching and increasing scale of circuit integration, has become a major problem. And furthermore, radiation noise coherent with clocking is a problem. As a technique of solving such problems as clock skew, increasing power consumption and radiation noise, asynchronous design has come into matter of attention.